1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to coordinating speculative and committed state register source data and immediate source data in an a processor performing speculative out-of-order instruction execution.
2. Background
Typical prior computer processors implement in-order instruction execution pipelines. An in-order processor usually fetches an instruction stream from a memory, and executes each instruction in the instruction stream according to a sequential program order. Such in-order instruction execution ensures that data dependencies among the instructions are strictly observed.
A processor may perform out-of-order instruction execution to increase instruction execution performance. Such a processor executes ready instructions in the instruction stream ahead of earlier instructions in the program order that are not ready. A ready instruction is typically an instruction having fully assembled source data and available execution resources. Typically, the source data or operands for an instruction comprises the contents of one or more internal processor registers, or immediate source data, or a combination thereof.
Such out-of-order execution improves processor performance because the instruction execution pipeline of the processor does not stall while awaiting source data or execution resources for a non ready instruction. For example, an instruction in the instruction stream may require source data from a processor register, wherein the processor register is loaded by a pending external memory fetch operation. Such an instruction awaiting the results of the external memory fetch does not stall the execution of later instructions in the instruction stream that are ready to execute.
A processor may also perform speculative instruction execution to increase instruction execution performance. Such a processor typically determines a speculative execution path through a program by predicting the result of branch instructions. Such a processor fetches an instruction stream from a memory, predicts a branch result for each branch instruction, and continues fetching and executing the instruction stream according to the predicted branch result. Such speculative execution increases processor performance because the instruction execution pipeline does not stall during the resolution of branch instructions.
A processor that performs both speculative and out-of-order instruction execution generates speculative result data in an out-of-order sequence in relation to the original program order. The result data is out-of-order because the instructions that cause generation of the result data are executed out-of-order. The result data is speculative until the branch prediction that caused speculative execution of the instructions is resolved.
Such a speculative out-of-order processor requires a mechanism for coordinating the source data required for execution of each instruction in the instruction stream. The required source data for an instruction may be immediate source data which is available with the instruction. The required source data for an instruction may be result data generated by execution of other instructions. Such result data may be assigned to a speculative state resource or a committed state resource. The speculative result data in the speculative state resource is not valid until the instructions generating the source data have completed execution. The speculative state result data becomes committed state result data after program exceptions and branch predictions are resolved.